Field of the Invention
The present invention relates to a memory cell configuration in which an outdiffusion of a dopant from the bit lines is largely avoided.
A memory cell array constitutes a matrix-like configuration of memory transistors in each of which, at a top side of a semiconductor body or substrate, a channel region is present between source/drain regions. The channel region is driven by a gate electrode isolated from the channel region by a gate dielectric.
A storage layer is present in the gate dielectric, the storage layer being provided for the programming of the respective memory cell. Such a storage layer may be, for example, an electrically conductive layer disposed in accordance with a floating gate, or a storage layer sequence provided for charge trapping of hot electrons from the channel (CHE), for example an oxide-nitride-oxide layer sequence (ONO layer sequence).
The gate electrodes are connected row-wise by word lines disposed parallel to and at a distance from one another; the source/drain regions are connected to one another column-wise by bit lines disposed parallel to and at a distance from one another. The word lines are preferably electrically conductive strips on the top side of the configuration. So-called buried bit lines formed as strip-type doped regions in the semiconductor material are suitable as bit lines. The buried bit lines thus directly connect the source/drain regions to one another, which source/drain regions are also formed as doped regions and may, in particular, constitute respective portions of the buried bit lines.
Since, in order to produce the bit lines, a dopant is introduced into the semiconductor material and the dopant outdiffuses from the original region in subsequent heat treatment steps in the production process of the memory cell configuration, the problem arises that this patterning of the memory cell configuration cannot be reduced to arbitrarily small dimensions. The formation of the buried bit lines is usually followed by process steps that are carried out at process temperatures of more than 600° C., e.g. oxidations, depositing of polysilicon, and annealing of implants for activation of the dopings. The thermal loading that occurs in this case leads to an outdiffusion of the dopants of the bit lines, which blur the original dopant profile and enlarge the relevant regions. That imposes technical limits on a scaling of the structure toward ever smaller dimensions. A desired setting of the dopant profile, in particular in the region of the pn junction of the source/drain regions toward the doped well of the semiconductor body, is possible only within limits; an abrupt transition of the dopant concentration cannot be realized.
In order to enable a memory cell array of this type to have a small structural width that is of or below the order of magnitude of the occurring outdiffusion of the dopant atoms from the buried bit lines, the individual memory cells may be formed as trench transistors. In the case of memory transistors of this type, the respective gate electrode is situated in a trench produced in the semiconductor material between the doped source/drain regions. Only the outdiffusion of the dopant from the source/drain regions downward in the direction of the substrate is significant in the case of a structure of this type. If the trenches are deep enough, so that the trench bottom lies deeper in the substrate than the boundary of the outdiffused dopant, it is the case in the memory transistor thus patterned that at least the lateral structural width determined by photolithography is smaller than the outdiffusion length. As a result, it is possible to achieve a miniaturization of the memory cells, but the blurring of the dopant profile in the region of the pn junction cannot be prevented.